1. Field of the invention
This invention relates to Non-Volatile Dynamic Random Access Memory (NVDRAM) and the methods of operations. In particular, a semiconductor NVM cell and a conventional DRAM cell are incorporated to form a single NVDRAM cell. The NVDRAM cell configuration of the invention is capable of separating the low voltage operation of DRAM and high voltage operation of semiconductor NVM. Thus, the operations of the NVDRAM cells of the invention are also simplified and various voltage powers can be turned on and off according to the operational modes for lowering chip power consumption. The NVDRAM cell of the invention has read/write speed of the conventional DRAM with non-volatile memory capability as well.
2. Description of the Related Art
Semiconductor memories have been broadly applied to electronic systems. Electronic systems require semiconductor memories for storing instructions and datum from the basic functions of controls to the complex computing processes. Semiconductor memories can be categorized into volatile memories and non-volatile memories. The volatile memories including Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM) lose their stored datum after the memory's powers are turned off. While the semiconductor non-volatile memories such as Read Only Memory (ROM), Electrical Erasable Programmable Read Only Memory (EEPROM) and flash still keep their stored datum even without the memory power.
In areas of electronic system applications, DRAM has become the memory of choice for storing large datum due to its high read/write speed, high density, and low cost. An active electronic system applies the datum from DRAM for instruction execution and information inputs and stores back the new datum to DRAM for further operations. In addition, when the power for an electronic system is turned on, the system would require having initial datum for instructions and information to operate. The initial datum is usually stored in a non-volatile memory device. An electronic system has to move the initial instruction and datum from a non-volatile memory device to a DRAM device before entering the system normal operations. The datum moving from a non-volatile memory device to a DRAM device has always occupied a major wait time for booting up an electronic system. On the other hand, for turning off electronic systems or power interruptions by a failure or a glitch, some critical datum in DRAM device can not be lost and need to be stored back to a non-volatile device for the use of next power-on. Thus, it shall be very desirable for electronic system memory applications to integrate an NVDRAM device capable of having the function of DRAM and the function of recalling and storing non-volatile datum.
In the development of NVDRAM, transferring charges between the storage node of DRAM capacitor and the charge storing material of a semiconductor non-volatile memory has been the main focus. For example, U.S. Pat. No. 3,916,390 to J. J. Chang et al. discloses a cell structure similar to the split-gate MNOS (Metal Nitride Oxide Semiconductor) non-volatile memory for backing up dynamic memory for a power failure (schematic shown in FIG. 1a); U.S. Pat. No. 4,055,837 to K. U. Stein applies the structure of Electrical Erasable Programmable Read Only Memory EEPROM (the schematic of one P-type access transistor and one non-volatile storage node as shown in FIG. 1b); U.S. Pat. No. 4,471,471 to D. J. DiMaria applies silicon-rich Double Electron Injection Structure (DEIS) stack to inject electrons to floating gate for non-volatile programming before the thin tunneling oxide become available (FIG. 1c); U.S. Pat. No. 5,331,188 to Acovic et al. applies three ploy-silicon layers for DEIS, and a thin tunneling oxide in between the first poly-silicon and the heavy doped P-type diffusion as the Single Electron Injection Stack (SEIS) for transferring charges between the floating gate and capacitor storage node (FIG. 1d).
As the oxide growth process has been improving reliable thin tunneling oxides required for transferring charges in-out of the charge storing material while maintaining the stored charges non-volatile become easily available for semiconductor non-volatile memory. In recent development of NVDRAM, U.S. Pat. No. 6,952,366, No. 7,072,213, and No. 7,319,613 to Forbes apply a Nitride Read Only Memory (NROM) cell for access transistor, and a storing capacitor (FIG. 1e); U.S. Pat. Nos. 6,996,007, 7,054,201, 7,099,181, and 7,224,609 to Ahn et al. apply nitride film and floating gate non-volatile memory cell for the access transistor, and a storing capacitor (FIG. 1f). Both NVDRAM approaches have achieved the most cell compactness of 1T1C (one transistor and one capacitor) configuration as that of conventional DRAM cell. Although the 1T1C configuration is the most compact form of NVDRAM cell the non-volatile access transistor, unlike the access transistor of the conventional DRAM cell, requires high voltage to operate not only for the charge transfer tunneling operations but also for accessing the capacitor storage node. Furthermore, since the thick film stacks from the control gate to the channel of a non-volatile Metal Oxide Semiconductor Field Effect Transistor (MOSFET) consist of coupling dielectrics, a layer of charge storing materials such as floating gate, nitride dielectrics, or nano-crystals, and a layer of tunneling oxide between ˜100 to ˜80 angstroms thick, the driving transistor performance of non-volatile MOSFET is much inferior to that of MOSFET (oxide thickness ˜30 angstroms) applied for the access transistors in modern DRAM. In dynamic memory mode the above mentioned 1T1C NVDRAM would have slower read/write access performance and require applying a higher gate voltage to access the capacitor storage node. The high voltage access also results in higher power consumption and longer switching time to turn on/off the access transistors for the dynamic memory read/write operations in comparison with the modern DRAM. Substitution of the access transistor for non-volatile MOSFET would sacrifice the performance of modern DRAM for speed and power consumption. In addition, for programming the 1T1C NVDRAM, the high voltage applied at the drain electrode of the non-volatile MOSFET connected to the storage capacitor may exceed the maximum dielectric field strength of the storage capacitor designed for low voltage operation in modern DRAM. This constraint has lead to more complicated and less efficient tedious programming schemes as disclosed in Forbes and Ahn.
In order to simplify the programming/erase operations for the non-volatile memory but not to compromise the DRAM performance of the low voltage operations, we have disclosed a new 2T1C (one non-volatile transistor+one access transistor+one storage capacitor) NVDRAM to operate exactly the same as DRAM for the random dynamic memory applications and to have the capability of fast recalling and storing non-volatile memory datum as well.